| csc 480
syllabus
homework
lab
etc
archive |
The archive of our class calendar is given below:
Tue Jan 6
- Lecture: Chapter 1
- HW #1 assigned
Thu Jan 8
Tue Jan 13
- Lecture: Chapter 2
- HW #1 due
- HW #2 assigned
Thu Jan 15
Tue Jan 20
- HW #2 due
- Lecture: Chapter 3
Thu Jan 22
Tue Jan 27
- HW #4 due
- Lecture: Chapter 5
Thu Jan 29
Tue Feb 3
- Midterm!
- 30 points, or 30% of your final grade
- 1 side of notes, closed book
- Covering Chapter 1-5
- Approx. 90 minutes
- Bring your logic templates
- Pre-midterm office hours: 5:00-6:15 Tuesday night or by appointment
Thu Feb 5
Tue Feb 10
- Lecture: Chapter 6
- Assigned: Homework #7
Thu Feb 12
Tue Feb 17
- Due: Homework #7
- Lecture: Chapter 10-1 through 10-3
- Lecture: Chapter 7
Thu Feb 19
Tue Feb 24
- Announcement: Sorry, no office hours before class today!
- New due date: Homework #8
- Lecture: Chapter 8
Thu Feb 26
- Due: Read Chapter 9
- Lecture: I'll take any questions on Chapter 9, and then
- Pop quiz: Chapter 9... bring one side of one page of notes,
worth 2 points (like a homework)
- Lab: Lab #8 - "Counting the
memories"
Tue Mar 2
- Lecture: Finish Chapter 8 binary multiplier example
- Lecture: Chapter 10
- Assigned: Homework #10
Thu Mar 4
- Lecture: Chapter 10
- Lab: Finish Lab #8
- Lab: Lab #9
Tue Mar 9
- Due: Homework #10
- Due: Grad student projects... Verilog or other EDA software
demonstrations
- Lecture: Verilog... Verilog
Overview
Thu Mar 11
Tue Mar 16
- Final exam
- 40 points, or 40% of your grade
- One side of one page of notes allowed, closed book
- Comprehensive with an emphasis on Chapters 6-10
- Two hour time limit
- Bring your logic templates, leave your calculators home
- I am (sigh) definitely available for Final Exam tutoring via
email or in my office... just contact me via email.
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