CSC 480 Homework

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Unless otherwise noted, each homework will be worth 2 points. We should have approximately 10 homework assignments over the term.

Go!

Homework #1

Chapter 1 problems due Tue Jan 13:

•  1-3, 1-7, 1-11, 1-12, 1-15, 1-16, 1-18, 1-22, 1-23

Solution set: Homework #1 solution set

Homework #2

Chapter 2 problems due Tue Jan 20:

•  2-2, 2-6, 2-8, 2-9, 2-10, 2-13, 2-15, 2-17, 2-20
•  Email me at wtkrieger@noctrl.edu a web site (keep it clean) or book that you would recommend to me. I will reply with my book/site recommendation. In addition to snarfing your cool ideas, I like to have your email handy.

Note! Most of these problems have multiple parts... you are only required to do the ceiling of 1/2 of the number of parts. For example, if there are 5 parts to the problem, then you must do 3 of them.

Solution set: Homework #2 solution set

Homework #3

Chapter 2/3 problems due Thu Jan 22:

•  2-23, 2-24, 2-27, 2-30
•  3-10, 3-16... please implement each design in gates and then also as a PLA.

Solution set: Homework #3 solution set

Homework #4

Chapter 4 problems due Tue Jan 27:

•  4-5... but don't follow their directions totally:
  •  (a) Build a 4-to-16 decoder using only 1 3-to-8 decoder, 16 2-input AND gates and an inverter.
  •  (b) Build a 4-to-16 decoder using the algorithm on page 149, with 2 2-to-4 decoders and some glue, that is.
•  4-12 (a) and (b)
•  4-22
•  4-25
•  4-29 (a)
•  4-30... also draw a diagram of the # inputs/outputs on the ROM.
•  4-31... express your PLA using the PLA programming table format
•  4-35... again use the PAL programming table format

Solution set: Homework #4 solution set

Homework #5

Chapter 5 problems due Thu Jan 29:

• 5-4
• 5-6
• 5-8 (b)
• 5-9
• 5-12... can you use an adder-subtractor to do this?
• 5-13

Solution set: Homework #5 solution set

Homework #6

Chapter 6 problems due Thu Feb 12:

• 6-1... you can use waveforms or draw the circuit multiple times showing signal transitions
• 6-5
• 6-8
• 6-9
• 6-16... this is a tricky one, so read it carefully. Try a gray code when doing your state assignment. Forget the reset in part (c).
• 6-23

Homework #7

Chapter 6 problems due Tue Feb 17:

• 6-4... On the SR flipflop, t_ch should (I think) be t_w, the minimum clock pulse width
• 6-19... this one gets a list of notes:
  • I believe a part of the problem is wrong as written in the book. Can you find the error or correct me?
  • Can you implement this machine using the Moore model?
  • You read the message word serially, one bit at a time, starting from the left.
• 6-25
• 6-26... only do parts (a) and (c). Also, please answer my excellent part (d):

4. Now that your part (a) design is complete, describe what happens to your circuit if it enters one of the don't care states. Is it good or bad?

Homework #8

Chapter 7 problems due Thu Feb 19:

•  7-5
•  7-21
•  7-22
•  7-23
•  7-27
•  7-28
•  7-31
•  7-32
•  7-33

Homework #9

Chapter 9 Pop quiz... Yow!

Homework #10

Chapter 8 and 10 problems due Tue Mar 9: 

•  8-2... this problem and the next three all munge the ASM given in Figure 8-19
•  8-3
•  8-8
•  8-9
•  8-13
•  8-14
•  8-15
•  10-9
•  10-10
•  10-13
•  10-15
•  10-16

Note on logic diagrams

I do not accept logic diagrams that are drawn by hand. This leaves you two choices:

• Use a program... there's a program call CircuitMaker that is nice and easy. Download (about 3MB) the "Student Version"; it's free. It's available at:

http://www.microcode.com

• Get a logic template... I prefer the old-fashioned template, but then, I'm old. the other advantage of a template that you can use them on lab and test problems. Don't go ordering anything right away... we'll talk about this on the first class. I found some at:

http://www.artstuff.net/timely_flow_chart.htm