CSC 480 Digital Logic & Computer Design

Spring 2006 term

It's all there... the syllabus, cool labs, homework, your class project, and everything else

"It's over Johnny"

CSC 480 grades are in and should be available on Merlin. Now? Soon?

If you like, you can email me or stop by for your grade info.

Thanks for a fun class, guys.

good luck... yow, bill

Final Exam... June 5

final... Final... FINAL...

•  The exam will be Monday, June 5 from 1:30 - 3:30 pm in our usual room.
•  It's worth 40% of your final grade.
•  The Final is comprehensive with a strong emphasis on the 2nd half material, including:
  • Chapter 6 Sequential circuits
  • Chapter 7 Register transfers
  • Chapter 8 Sequencing and control
  • Chapter 10: Computer Design Basics
  • Verilog
  • Your project
•  You may bring one side of one page of notes
•  We'll solve problems, eh.

Week 10... May 29-Jun 2

What's due:

•  Lab #8
•  Fri: Projects

Mon: No class on Memorial Day... Noctrl Holiday Schedule

Wed: Chapter 10 lecture.

Fri:  Final Exam preview and discuss projects... projects must be completed by midnight Friday.

Note: Out Final Exam will be Monday June 5 at 1:30 pm... Noctrl Final Exam Schedule

Week 9... May 22-26

What's due:

•  Mon: Project milestones
•  Fri: Lab #7

Mon: We'll review your project milestones from over the weekend. Then, I'll continue my lecture on Chapter 8 with our sequential binary multiplier example.

Wed: Project status and then probably one more lecture on Chapter 8.

Fri:  Project milestones, finish Chapter 8, and then start Chapter 10.

Oh yeah, no class on Memorial Day, Monday May 29: Noctrl Holiday Schedule

Week 8... May 15-19

What's due:

•  Wed: HW #7
•  Fri: Lab #8

Mon: Independent Project Monday... please work on your projects from 1:30-3:00 and then communicate to me the results of your labor, either via email or visit my office at 3:00. This will be your 1 point for the week... to further help motivate you. Let's get some project momentum going!

Wed: Verilog examples and your 5 statements/questions (your week 7 point). Start Chapter 8 prattling.

Fri: Chapter 8 lecture.

Week 7... May 8-12

What's due:

•  Mon: Lab #6... so we can catch-up
•  Mon: HW #6
•  Fri: Lab #7

Mon: Let's talk Verilog. I have a handout for you: Verilog Overview and a mini-assignment:

1. Please read the Wikipedia Verilog handout that I will give you
2. Do the tutorial at www.asic-world.com/verilog/veritut.html
3. And come to class Wednesday with 5 important things or questions you have about Verilog in the course of your reading mini-assignment.

Wed: Verilog and your mini-assignment. We'll start Chapter 7.

Fri: Finish off Chapter 7... hopefully. I'll check out your labs.

Please don't forget your project deadlines this week. thanks... yow, bill

Week 6... May 1-5

What's due:

•  Fri: Lab #5
•  Next Mon: Lab #6... so we can catch-up
•  Next Mon: HW #6

Mon: Finish up Chapter 6? We'll do lots of examples... this chapter is a lot of fun.

Wed: Return your midterm. We'll have lecture either on Chapter 6. Stay tuned. I posted HW #6, which will be due on Monday.

Fri: Project day

Week 5... Apr 24-28

What's due:

•  Mon: Homework #4 is due
•  Fri: Midterm exam!

Mon: Lecture on Chapter 6

Wed: I'll return your HW #4, and we'll do a midterm preview... maybe some more lecture on Chapter 6

Fri: The midterm.

•  30% of your grade
•  2 hours long... from 1:30 - 3:30
•  You can bring 1 side of 1 page of notes
•  Covers: Chapters 1-5, without any HDL stuff... focus on the homework problems
•  Jeez guys... Study!!!

Week 4... Apr 17-21

What's due:

•  Mon: Homework #3 is due
•  Mon: Please read and have "nice notes" on Chapter 4 Combinational Functions & Circuits
•  Fri: Read/notes for Chapter 5 Arithmetic Functions & Circuits
•  Fri: Lab #4 is due

Mon: I'll lecture on Chapter 4... please bring your notes and questions.

Wed: Lecture on Chapter 5... homework #4 is up and due next Monday.

Fri: Lecture on Chapter 5? Lab ? We'll see.

Week 3... Apr 10-14

What's due:

•  Mon: Homework #2 is due
•  Mon: Please read and have "nice notes" on Chapter 3 Combinational Logic Design
•  Fri: Lab #3 is due

Mon: I'll start in on Chapter 3. This is not as meaty as Chapter 2. Please show me your notes, as I'm not going to lecture on each nook and cranny.

Wed: Probably one more lecture on Chapter 3, then onto Chapter 4... HW #3 is posted. I added some fun, futuristic links on NRAM in the everything else page...

Fri: This is Good Friday, actually. I'll hold office hours from 1:30 - 3:00 in our classroom.

I'd love for the midterm to cover chapters 1-5 in our text... all the combinational stuff. You might call it a "goal" of mine. Ha!

Week 2... Apr 3-7

What's due:

•  Mon: Homework #1 will be due
•  Mon: Please read and have questions and nice notes on Chapter 2
•  Fri: Lab #2 will be due

Mon: We'll begin Chapter 2, I'll be adding the Quine-McCluskey algorithm to Chapter 2 once we get through K-maps

Wed: more Chapter 2 lecture, questions, problems... I have posted HW #2

Fri: I'll peek at your labs, and then...

Week 1... Mar 27-31

Quote of the Day:

Mon: Introduction and stuff, Chapter 1 blathering and a couple examples

Wed: I'll take your Chapter 1 questions and move on to Chapter 2. Make sure that you have read Chapter 2 before lecture. We'll do some problems together.

Fri: We'll do Lab #1 together. Hey make sure that you have room in your backpack (or whatever) for your LD-2 Pencil Box Logic Designer kit. It's about the size of our text.

Week 0

Before our first class, you have two assignments:

1. Please email me your feedback and any questions on the syllabus and other stuff I have posted so far.

2. Please read Chapters 1 and 2 from our text before the first class.

thanks... yow, bill

PS - Don't print out all the lab stuff, I'll probably give you each a hardcopy myself. What a nice guy!