CSC 480 Project

Project description...

The project is worth 20 points, so I expect it to be fairly interesting and involved.

Description

You propose a project, and we'll go from there. Here are some of the fun fun fun ideas that I have:

•  Design a circuit using an HDL like Verilog (probably) or VHDL (probably not)

•  Explore and use an Electronic Design Automation (EDA) program. I have some EDA software ideas listed at the end of this page.

•  Write your own little EDA program... for example, you could implement the Quine-McCluskey algorithm.

•  Learn an advanced topic, such as state assignment, simulation, HDL's, etc. I have another textbook with some advanced topics you can borrow.

Let's agree that you'll have a project topic selected by week 6, after the midterm.

Deliverables

•  Present your results to the class... during the last week of class.

•  Present your results to me in the form of a report or a demonstration.

EDA Software

There's a lot of fun, free software out there. Unfortunately, I wouldn't include the software in our textbook in that group. It's certainly free (for those of us who purchased the book), but it big, bulky and had much of the functionality drained from its veins (like working with HDLs). You can try it if you want, however.

Logic minimization

A program named Espresso is one of the ground-breaking logic minimization programs from back in the day. You could download it, learn it, and then use it on a number of examples. I found a copy at:

http://www.csc.uvic.ca/~csc485c/espresso/instructions.html

HDL simulation

I haven't tried these guys (or it was a long time ago), but here are some programs that simulate (or run) Verilog HDL designs:

•  Verilogger is a complete Verilog simulation environment... I think that evaluation copies are free...  www.syncad.com/vlg_form.htm 
•  The Icarus simulator doesn't look as strong as Verilogger, but who knows... www.icarus.com/eda/verilog/ 
•  LogicSim also has a free trial version, I believe... http://www.logicsim.com/

Verilog

There are a number of sites that index "free" tools for Verilog:

•  www.verilog.com - try "links" link

•  www.veripool.com - looks pretty good

•  www.verilog.net - try "free tools" link

•  www.geda.seul.org - sort of a Gnu for EDA software

You can troll these sites looking for interesting software. Another possible project is to

Finite State Machines

Some programs focus on automating the process of designing finite state machines. Here are some:

•  http://mufasa.informatik.uni-mannheim.de/lsra/projects/fsmdes/ - FSM Designer... it's free, but I haven't used it. It's written in Java.

•  http://fsme.sourceforge.net/ - a guy called the Finite State Machine Editor

When all else fails, google it.

that is all... yow, bill