Wed May 17, 2006

•  7-5... bit masks
•  7-22... a couple basic ones
•  7-23
•  7-31... a couple bus problems
•  7-32

Mon May 8, 2006

•  6-1... simulate a latch, like in class
•  6-4... understanding setup/hold violations
•  6-5... sequential design, start with flipflop equations
•  6-8... trace/simulate a sequential design
•  6-9... state table to state diagram
•  6-16... sequential design word problem, sweet!
•  6-23... sequential design, start with state diagram
•  6-26... designing a counter, just do parts a) and c)

Yes, I know we skipped HW #5... I'm keeping up with the chapters in the book. Sorry. Please drive through... yow, bill

Mon Apr 24, 2006

From pages 192-195

•  4-5... building decoders
•  4-12... building muxes
•  4-22... logic design with decoders
•  4-25... logic design with muxes
•  4-29 a)... logic design with ROMs
•  4-30... logic design with ROMs
•  4-31... logic design with PLAs, please use our nice file format
•  4-35... logic design with PALs

From pages 236-238

•  5-4... 2's complement
•  5-6... 2's complement
•  5-8 b)... logic design with 2's complement
•  5-12... design!
•  5-13... design!

Mon Apr 17, 2006

From pages 134-139:

•  3-4... path delay calculation
•  3-15... a fun design problem
•  3-16... more fun, can you also please implement this using a PLA in the format we discuss in class.
•  3-20... DeMorgan shenanigans mostly
•  3-21... a technology mapping problem, just have fun with it and appreciate the trade-offs and how difficult a challenge this is to do optimally for even this tiny example. You must use inverters to complement inputs as necessary. See the And-Or-Invert gate at only 2.25 area? Yum!
•  On page 108, a truth table solution for the BCD-to-7-segment problem is given. Tell me:
  •  How would you implement this using a ROM?
  •  Draw a black box of your ROM?
  •  What values would be burned into the ROM at each address?

Mon Apr 10, 2006

So, from pages 81-85:

•  Boolean algebra... 2-2, 2-6
•  DeMorgan... 2-8, 2-9, 2-10
•  Use your new logic template... 2-13
•  K-maps... 2-15, 2-17, 2-20, 2-24
•  Quine-McCluskey... 2-20 a) using Q-M, check against K-Map
•  SOP and POS... 2-23
•  Multi-level optimization... 2-27
•  XOR and Boolean algebra... 2-30

Okay, on problems with more than 2 parts, you only have to do the ceiling of the number of parts divided by two. In other words, just do half the parts.

thanks... yow, bill

Mon Apr 3, 2006

•  1-3, 1-7, 1-11, 1-12, 1-15, 1-16, 1-22, 1-23