2. IJVM Datapath Notes
These notes elaborates Figure 4-1 "The datapath of the example
micro-architecture used in this chapter" on page 233 of our text.
3 types of datapath components: registers, ALU, and shifter.
Registers
All registers are 32 bits wide. The registers mean:
| Register |
Description |
| SP |
stack pointer |
| LV |
frame pointer |
| CPP |
constant pool pointer |
| TOS |
holds the value at the
top of the stack |
| OPC |
scratch register for
intermediate values |
| H |
holding register for the
ALU "A" input |
| MAR |
memory address register,
holds addr of mem ref |
| MDR |
memory data register,
holds data read to/from mem |
| PC |
program counter, memory
address of next instruction |
| MBR |
memory register B, holds
instruction at PC location |
Most register values can be loaded (read) onto the B bus, and changed/written
from the C bus value. Some exceptions are:
- MBR can only be written from memory
- MDR can be written from memory or bus C
- MAR,
MDR, and
PC values are used by memory
- MAR register is not connected to B bus
- MBR uses only 1 byte (of 4), holds 1 byte opcode
ALU
ALU is as shown in Figure 3-19 on page 156. This one bit slice is replicated
32 times to handle our 32 bit quantities. 2's complement is used for negative
numbers. Each slice has 2 function inputs, F0 and F1:
| F0 F1 |
Function |
| 0 0 |
A and B |
| 0 1 |
A or B |
| 1 0 |
not B |
| 1 1 |
A + B |
The datapath ALU has 6 control inputs: F0, F1 (as above) and 4 others:
- ENA - enable A input, or use 0 if false
- ENB - enable B input, or use 0 if false
- INVA - invert A input, or just use A if false
- INC - increment ALU result if true by forced carry into lowest bit
See Fig 4-2 on page 234 for a sampling of "useful" 6 bit control combinations.
Shifter
2 control bits:
- SLL8, "Shift left logical 8 bits" - shift left 8 bits, filling
least significant bits with 0's
- SRA1, "Shift right arithmetic 1 bit" - shift right 1 bit, leave
most significant bit unchanged
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