3. IJVM Micro-instruction Format Notes

The notes elaborate Figure 4-5 "The micro-instruction format for the Mic-1" on page 240 of our text.

The IJVM micro-instruction word contains 36 bits. These are:

• Addr (9 bits) - the address of the potential next micro-instruction
• JAM (3 bits) - determines how the next micro-instruction is chosen
• ALU (8 bits) - 2 ALU function bits (F0, F1), 4 ALU modifier bits (ENA, ENB, INVA, INC), and 2 shifter bits (SLL8, SRA1)
• C bus (9 bits) - selects registers (yes, it can be more than one) that are written from the C bus
• Mem (3 bits) - selects memory functions: read, write, and fetch an instruction
• B bus (4 bits) - selects one register as the source for the B bus; 9 register choices are encoded into 4 bits

Also:

• Some of these control signal aren't explicitly drawn on our datapath figure 4-1
• Note how memory references work:
  • Datapath cycle N - assert a memory read signal to start read at end of cycle
  • Datapath cycle N+1 - one cycle to access memory value, value stored in MBR or MDR at end of cycle
  • Datapath cycle N+2 - memory value is now available in MBR or MDR
• There are important, simplifying assumptions made in memory access. I can't improve on the explanation on page 239: "The assumption that memory takes one cycle to operate is equivalent to assuming that the level 1 cache hit rate is 100%. This assumption is never true, but the complexity introduced by a variable-length memory cycle is more than we want to deal with here." Amen.
• With these control signals, only 1 register may drive the B bus, but many registers may be written with the value on the C bus.
• JAM bits determines whether the next micro-instruction is PC++ (normal operation) or a jump to an instruction somewhere else in memory