CSC 480 Lab #3

"XOR-scuse me" Lab

Purpose

bullet Become familiar with and use the exclusive-or (XOR) gate to solve logic design problems

Components used

bullet 7400 quad 2-input NAND
bullet 7486 quad 2-input XOR

Pin layouts for these chips are attached.

Lab Procedure

From our last lab, I think we can improve our performance by:

  1. Better lab reports - Clear, organized lab reports are required.
  2. Improve logic diagrams - Keep your input and output ordering consistent and logical. Label your circuit diagrams using the S1-SN input switches and the L1-LN output lights that you are using.
  3. Improve design process - For many of you, the put everything together and then see if it works methodology will be slow and error-prone. You can put parts of your circuit together, test it and then continue.
  4. Better debugging - Use LED outputs to debug intermediate points in your circuit.
  5. Safety - And again, for your safety... unplug the logic box while you are working on it!

Lab Problems

This lab focuses on the design of logic using XOR gates... please complete each of the following parts:

  1. Please try the following special cases with 2-input XOR gates:
    bullet Tie one of the inputs of the XOR gate to logic '1' and exercise the other input
    bullet Tie one of the inputs to logic '0' and exercise the other input
    bullet Tie the inputs together (both inputs the same value)

    For each special case, show the truth table, circuit diagram and comment on what common Boolean operation each case mimics.

  2. What function is created when taking the dual of a 2-input XOR Boolean operation? Implement your result with only 2-input XOR gates. Show the Boolean gymnastics you needed to do this. What is the relationship of this circuit to a plain, old 2-input XOR?

    Note: The final two steps aren't hard, rather a bit tricky... XORs "bend" many of our beloved logic design tools, namely Boolean algebra and K-Maps. You will have to recognize the XOR "pattern" with either your equation (A'B + AB') or K-Map (the checker-board pattern) during simplification. The next two problems exhibit these patterns.

  3. Construct a 3-input XOR gate with 2-input XOR gates. Show the Boolean algebra work to justify your design. The trick: you can substitute the XOR operator any time you see the pattern (A'B + AB').
  4. Construct a full adder circuit using 2-input XOR gates and 2-input NAND gates. Show the K-Map for each output to justify your design. The truth table for a full adder is:
    Inputs Outputs
    X Y Z Carry Sum
    0 0 0   0 0
    0 0 1   0 1
    0 1 0   0 1
    0 1 1   1 0
    1 0 0   0 1
    1 0 1   1 0
    1 1 0   1 0
    1 1 1   1 1

Deliverables

For each lab problem, the following items are required:

bullet A brief summary of the problem you are solving
bullet A truth table (or SOP/POS form if appropriate) of the circuit that you are building
bullet Show the steps (if any) you took to minimize or derive your circuit, such as: K-Maps, Boolean algebra, DeMorgan's Theorem, Consensus Theorem, etc.
bullet A logic diagram of the circuit that you are building... please use your templates!
bullet Show me your circuit