Study Sheet - Chapter 5

Disclaimer: This study sheet covers important terms and concepts that I found in the text. The absence of a specific item in the text from this list does not mean that you are not responsible for knowing it. Veni vidi vichyssoise... I came, I saw, I had cold soup.

5.1 Overview

ISA is "the architecture"... the level between the micro-architecture level and the assembly language level.

Terms:

You should understand:

• the difference between general-purpose and special-purpose registers
• Pentium 4 ISA:
  • modes: real mode, virtual 8086 mode, protected mode
  • frame pointer, stack pointer
  • registers
• UltraSPARC:
  • 64-bit machine
  • RISC, load-store architecture
  • 32 64-bit registers, register windows
  • parameter passing, local variables, return values all in registers
• 8051
  • Program memory, data memory, ROM, RAM
  • 8 8-bit registers, 4 sets of them though
  • some single bit memory access, instructions
  • accumulator architecture

5.2 Data Types

Chapter lite:

• There are numeric (int, float, signed, unsigned, BCD, etc.) and nonnumeric (characters, bitmaps, etc) data types.
• Uses IEEE floating-point standard 754 (that we learned last time, eh)
• 8051 supports a bit data type.

5.3 Instruction Formats

Format choices:

• size
• fixed vs. variable length
• zero, one, two, and three address instruction
• impact of operand size on register/memory addressing
• expanding opcodes

Pentium 4: "highly complex and irregular", variable length, expanding opcode, scale-index-base (SIB)

UltraSPARC: fixed length, 3 address (usually)

8051: variable length (1, 2, 3 bytes), 1-address instrs (usually) with accumulator architecture

5.4 Addressing

Go [with Intel assembly example of each]:

• immediate - constant [movl $17, %eax]
• direct - fixed memory location known at compile time, global [MIN: .long 0; movl MIN, %eax]
• register - use value in register [movl %ebx, %eax]
• register indirect - memory address in register [movl (%ebx), %eax]
• indexed - memory address plus constant [movl 8(%ebp), %eax]
• based-indexed - index plus a base in registers, SIB [movl 8(%ebp, %ebx, 4), %eax]
• stack

You should know how to do these in Intel assembly (again, "highly irregular") as I show above.

5.5 Instruction Types

Go:

• data movement - register to memory and visa versa, move, load/store
• dyadic - 2 operands, Intel assembly
• monadic - 1 operand, increment/decrement, shift, accumulator math, push/pop
• comparison and conditional branching - jump
• procedure call - call, return, uses stack
• loop control - specialized branch/jump
• input/output - interrupts, traps, very specialized

Know how Intel assembly instructions work, of course.

UltraSPARC: load/store architecture, "CC" instructions to update PSW

8051: accumulator architecture, simple instruction set

5.6 Flow of Control

Go:

• normal flow - IP = IP++
• procedure call - stack, procedure prolog, epilog
• know that there's nothing special about recursive procedures... they're handled just like the rest of our procedure calls
• coroutines
• traps, interrupts, and the difference between the two
• interrupt vector,
• transparency - life same after an interrupt

Know how Intel assembly instructions work, of course.

UltraSPARC: load/store architecture, "CC" instructions to update PSW

8051: accumulator architecture, simple instruction set