Study Sheet - Chapter 3

Disclaimer: This study sheet covers important terms and concepts that I found in the text. The absence of a specific item in the text from this list does not mean that you are not responsible for knowing it. Giddy-up!

We covered sections 1 through 6 in Chapter 3.

1. Gates and Boolean algebra

Terms:

transistor collector base emitter
gates inverters inversion bubbles  
Boolean algebra truth table complete duals
Boolean identities      

You should understand:

  • The basics of transistors and how they work
  • The 5 basic gates (not, nand, nor, and, or) and their truth tables
  • Manipulating Boolean equations: equations, truth tables, circuits, you should be able to convert from any of these forms to any other
  • The identities of Boolean algebra (ala Figure 3-6, page 144)
  • Converting Boolean equation to its dual
  • Why the combination of nand/nor gates are complete
  • The exclusive-or (XOR) function

2. Basic digital circuits

Terms:

integrated circuits (ICs) Dual inline packages (DIPs) gate delay combinational circuit
multiplexor (mux) demultiplexor (demux) decoder comparator
Programmable Logic Arrays (PLAs)      
shifter adder half adder full adder
ripple carry adder Arithmetic Logic Unit (ALU)    
clock clock cycle time rising edge falling edge

You should understand:

  • Construction and operation of:
    • N-to-1 mux
    • 1-to-N demux
    • M-to-N decoder
    • N bit comparator
    • PLA's
  • Construction and operation of the arithmetic circuits, including:
    • shifter
    • half adder
    • full adder
    • ALU
    • replicating single-bit adders into an N-bit ripple-carry adder

3. Memory

Terms:

latch flipflop register  
SR latch clocked SR latch D latch D flipflop
edge-triggered level-triggered    
tri-state buffer active high active low  
chip select (CS) write enable (WE) output enable (OE)  
RAM SRAM DRAM SDRAM
Fast Page Mode (FPM) Extended Data Output (EDO) Double data rate (DDR)  
ROM PROM EPROM EEPROM
flash memory      

You should understand:

  • The construction of memory using gates: 1) starting with SR latch, 2) adding a clock, 3) combining SR inputs into a D latch, 4) changing clock to edge-triggered to create a D flipflop
  • Tracing how an SR latch works
  • The difference between a latch and a flipflop, between level-triggered and edge-triggered
  • How memory is organization: the number of address bits required, word size, row/column addressing, tri-state outputs, active high vs. active low
  • The RAM/ROM alphabet soup and the difference between each device, the table on page 173 is a good summary
    • the difference between RAM and ROM
    • the difference between "dynamic" and "static" RAM
    • and so on...

4. Chips and Buses

Terms:

pinout bus master slave
synchronous bus asynchronous bus bus arbitration daisy chaining

Go:

  • 6 flavors of pinouts: bus control, interrupts, bus arbitration, coprocessor signaling, status, miscellaneous
  • Bus master/slave examples
  • Difference between a synchronous and asynchronous bus

5. Example CPU chips

Pentium 4 trivia:

  • backward-compatible to the Intel 8088
  • 32-bit machine, 55 million transistors, 3.2GHz, line width of 0.09 micron
  • pipelined micro-architecture
  • hyper-threading with two sets of registers to swap between two programs quickly
  • consumes 60-80 watts of power
  • memory bus for DRAM and PCI bus for I/O devices

UltraSPARC III trivia:

  • 64 bit machine
  • Risc architecture
  • have about the same power consumption as P4

8051 trivia:

  • 8 bit machine
  • CPU for embedded applications... hence 32 I/O lines

Know the important differences between these 3 CPU's.

6. Example buses

ISA bus:

  • "Industry Standard Architecture" bus
  • Old, IBM bus turned into industry standard
  • 16 bit bus
  • EISA (Extended ISA) is 32 bit version

PCI bus:

  • "Peripheral Component Interconnect" bus
  • Intel-developed and placed into public domain
  • Multiple bus architecture: ISA, PCI, main memory bus
  • Bridge chip to communicate between different buses

PCI Express bus:

  • point-to-point serial connections with devices
  • packet communication, protocol stack

USB bus:

  • Low cost
  • For low-speed devices: mouse, keyboard, etc.
  • "root hub" controls communication
  • Faster USB 2.0 now