4. IJVM Mic-1 Architecture Notes

These notes elaborate Figure 4-6 "The complete block diagram of our example micro-architecture, the Mic-1" on page 214 of our text.

The diagram contains our datapath and new hardware to control the datapath. These elements are:

• The control store is a ROM holding the micro-program for the machine. The size of the ROM is 512 words by 36 bits/word. This means that our micro-program can include a maximum 512 micro-instructions.
• A 4-to-16 decoder to decode the B bus signal, deciding which register will drive the B bus
• The MIR (micro-instruction register) contains the current micro-instruction to execute
• The MPC (micro-program counter) is similar to the PC register for our instruction set; it holds the ROM address of the next micro-instruction to execute.
• The box labeled High bit processes the N and Z outputs from the ALU to determine the highest order bit in the next micro-instruction.
• That O box below the MPC register is an 8-input OR gate. If JMPC is 1, then MBR is OR'd with the lower 8 bits of Addr to get the next micro-instruction address in MPC.

Some observations about the diagram:

• Notice the light dotted line around MAR, MDR, PC, MBR... these are the only registers involved in memory read/write. A "fetch" is a memory read of the next instruction at location PC  into MBR.
• The clock is not shown.

The next micro-instruction

The most complex or subtle part of the machine operation is determining the next micro-instruction to be executed.

• Remember, the next micro-instruction will be placed in MPC prior to the next machine cycle
• If JMPC is 0, then MPC set to the value of Addr. This Addr value is the "next address" field of the current micro-instruction being executed. Typically, this just increments the address to execute the next micro-instruction in a function, or it is a jump to a different part of the micro-program.
• If JMPC is 1, then MPC is set to the opcode stored in MBR. This means that a new opcode is loaded and we'll start executing micro-instructions from there. This also means that the opcode must be chosen to correspond to the ROM address of the micro-instructions that implement that opcode.
• When JMPC is 1, typically the value of Addr is 0x000 or 0x100 because that value is OR'd with the MBR address. In other words, the if a micro-instruction knows it's going to ask for the next opcode in MBR, then it will set its own "next address" to be 0.

Each machine cycle begins with the falling edge of the clock. Let's look at the sub-cycles within a single machine cycle: 

1. MIR is loaded with the micro-instruction stored at ROM address MPC. 
2. With a micro-instruction now available in MPC, one register value is selected to drive the B bus, making the inputs to the ALU avaiable.
3. The ALU and shifter component crunch and place the output on the C bus. The N and Z ALU signals are also set.
4. Load selected registers with the value on the C bus and also the N and Z flipflops on the rising edge of the clock.

After sub-cycle 4, the impact of the current micro-instruction is reflected in all register and flipflop outputs. With these values, the ROM address of the next micro-instruction is determined and "stored" in MPC. As our text points out, MPC isn't really there... the address just flows into the ROM.