Lecture Figures

This page contains references to all figures in the text that I thought were important enough to specifically go through in lecture.

The book's figures (provided by the publisher) are organized by chapter. I don't have access to an Adobe editor, just the reads, so I haven't figured out how to pull these figures out into individual files. Any ideas, let me know.

Appendix A/B

There figures for the appendices are not available (for some reason).

Lecture references:

• Figure A-7, page 639 - a table showing the representation of many 8-bit negative numbers in signed magnitude, 1's complement, 2's complement and excess-128 notation

Chapter 1

The figures: Chapter 1 figures

Lecture references:

• Figure 1-2, page 5 - the six levels of computer organization. This organization defines the structure of our text.
• Figure 1-5, page 18 - the Von Neumann machine... the basis for all computer architectures today
• Figure 1-11, page 32 - a graph showing Moore's law applied to Intel processor chips. Processor size has roughly doubled every 18 months. Will this continue?

Chapter 2

The figures: Chapter 2 figures

2.1 Processors lecture:

• Figure 2-1, page 40 - a basic computer organization and and the organization of Chapter 2, which is an overview of the basics of these 4 areas.
• Figure 2-2, page 41 - a basic datapath
• Figure 2-3, page 43 - the algorithm (in Java) of the operation of the basic datapath above. Please note that the statement PC = PC + 1 is not correct, the PC (Program Counter) may be set to some other value as in a conditional or loop statement.
• Figure 2-4, page 50 - an example of instructions traveling through a 5-stage pipeline. Remember the "cake assembly line" analogy. The 9 instructions in the example complete in 13 time units (with parallelism), rather than 45.
• Figure 2-5, page 51 - a dual 5-stage pipeline, ala the u and v pipelines found in the Pentium architecture. While the u pipeline can execute any arbitrary Pentium instruction, the v pipeline can only execute simple integer instructions. This restriction is done to lower costs.

2.2 Primary memory lecture

• Figure 2-11, page 59 - comparison of big endian and little endian byte ordering
• Figure 2-12, page 60 - conversion of big endian to little endian and visa versa, this conversion can only be made by knowing the structure of the data stored in memory
• Figure 2-13, page 62 - this table lists the number of check bits needed for a given data word size

2.3 Secondary memory lecture

• Figure 2-18, page 69 - memory hierarchy pyramid, top of pyramid is fast, expensive memory with speed and price per bit decreasing as you travel down the pyramid
• Figure 2-19, page 70 - illustration of the physical layout of a disk drive
• Figure 2-23, page 79 - the RAID levels 0-5, you should know each
• Figure 2-24, page 81 - illustration of the physical layout of a CD

2.4 Input/output lecture

• Figure 2-37, page 103 - illustration of how a laser printer works: 1) charge drum, 2) un-charge portions of drum with laser, 3) toner attracted to charged portion of drum, 4) roll drum over paper, 5) clean drum... repeat

Chapter 3

The figures: Chapter 3 figures

3.1 Gates and Boolean algebra lecture

• Figure 3-1, page 118 - I've already described the basics of transistors and how these "electronic switches" are the basis for all the computer technology we'll talk about this term.
• Figure 3-2, page 119 - five basic gates that comprise logic gates and their truth tables
• Figure 3-6, page 126 - Boolean algebra identities
• Figure 3-7, page 126 - duals created using DeMorgan's Law, nand/nor gates

3.2 Digital logic circuits

• Figure 3-10, page 129 - an SSI integrated circuit, a DIP
• Figure 3-11, page 131 - an 8-to-1 mux example
• Figure 3-13, page 133 - a 3-to-8 decoder example
• Figure 3-14, page 134 - a 4-bit comparator example
• Figure 3-19, page 138 - 1-bit ALU
• Figure 3-20, page 139 - 8-bit ALU comprised of 8 1-bit slices

3.3 Memory

• Figure 3-22, page 141 - SR latch circuit that is a basic building block of digital memory circuits
• Figure 3-23, page 142 - clocked SR latch, add a clock input to the SR latch so that changes in S or R inputs is only accepted when the clock is '1'
• Figure 3-24, page 143 - clocked D latch, combine SR inputs into one D input: D and D'
• Figure 3-26, page 145 - D flipflop, a pulse generator is added to the clock input which will make the flipflop edge-triggered rather than level-triggered
• Figure 3-29, page 148 - a 4 word x 3 bit memory, the important thing about this example is to be able to understand its structure and what each input/output is there for, note the tristate output buffers!
• Figure 3-30, page 150 - explanation of a tristate output, when the "control" input is low, the outputs are virtually disconnected
• Figure 3-31, page 151 - 2 ways of organizing a 4 M-bit memory, the 4M x 1 bit memory is addressed in two steps, row (by selecting RAS) and then column (CAS) which is why the chip doesn't have 22 address bits
• Figure 3-32, page 154 - summary table of all the memory flavors (and alphabet soup) discussed in the section

3.4 CPU chips and busses

Chapter 5

The figures: Chapter 5 figures

Pentium-related stuff:

• Figure 5-2, page 307 - Pentium architecture is little endian, and words can be non-aligned as shown in the example
• Figure 5-3, page 313 - registers in the Pentium architecture, note the way that EAX-EDX registers are sliced into 32-bit, 16-bit and 8-bit quantities
• Figure 5-6, page 320 - data types supported by the Pentium
• Figure 5-12, page 326 - example showing how an expanding opcode works, increasing opcode bits at the expense of address bits
• Figure 5-13, page 328 - shows the format of a Pentium 2 instruction, which is a very large and messy venture. Our book doesn't show a complete opcode encoding, so we won't do it either.
• Figure 5-17, page 335 - a "generic" assembly code (in Pentium style, however) example showing each of the 4 simplest addressing modes
• Figure 5-18, page 337 - a "generic" assembly code example showing the "indexed addressing" addressing mode.
• Figure 5-33, page 361 - a listing of selected Pentium instructions; we will refine this and explain it better later