CSC 480 Final Exam Study Sheet

The final is not comprehensive and will focus on Chapters 8-10, and some of Chapter 7. You may, of course, be called upon to exercise the logic design skills you learned in Chapters 1-6 to complete a design task during the final exam.

Chapter 8 - Sequencing and Control

This chapter is the kissin' cousin to Chapter 7, Dataflow. The focus is designing circuits to control datapath elements. You should be able to:

	Create a Algorithmic State Machine (ASM) from a problem description
	Analyze and understand an existing ASM
	Create a state diagram and/or state table from an ASM
	Understand the book's control example: a binary multiplier
	Know the two type of control unit designs: hard-wired and microprogrammed
	Create/analyze a hard-wired, one flipflop per state control unit
	Create/analyze a hard-wired, decoder-based control unit
	Create/analyze a microprogrammed control unit
	Understand Mano's "simple computer architecture", diagrammed on p. 430
	Understand the changes to the "simple" model for multi-cycle instructions

Chapter 9 - Instruction Set Architecture

This chapter defines assembly language instructions commonly found as part of a computer instruction set. You should know:

	The basic operation cycle of the computer (7 steps defined on p 469)
	The different operand addressing schemes (0, 1, 2 and 3 address instructions) available and their impact on the architecture
	The different addressing modes available
	The difference in the properties of a RISC and CISC architecture
	The various instruction types defined in the chapter (data transfer, data manipulation, etc)
	How floating point numbers are handled, including bias exponents and the IEEE format

Chapter 10 - CPU Designs

We explored two CPU designs:

A CISC machine with microprogrammed control
A RISC machine pipelined and with hard-wired control

You'll be asked to either create or analyze:

An instruction set and format

Assembly instructions for a computer

Addressing modes (again)

Datapath setup for a computer

Control setup for a computer

Microprogramming setup for control, including:

	Control word definition and format
	Instruction decoder
	Using a control ROM to store microprograms
	Writing and interpreting microprograms

Comparison of the CISC and RISC architectures

Please note: You will not be tested on the issue of data hazards in a pipelined design.

Chapter 7 - Register Transfers & Datapaths

The focus of the final exam is Chapters 8-10, but Chapter 7 is integral to these last chapters, so here we go. You should know:

	Control/Datapath model
	RTL operations: transfer, arithmetic, logic and shift
	Datapath structure: Reg file, Function unit, muxes
	ALU: adder + logic structure,
	Shifter: vanilla, barrel shifter
	Control word
	Pipelining: the basic concept, pipelining speedup equation