For the latches and flipflops, you should know the basic design (SR latch is two cross-coupled NOR gates), basic operation (simulate different logic values on each like we did on the board), and its truth table.
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SR latch |
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S'R' latch |
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SR latch with control |
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D latch |
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Master-slave flipflop |
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Edge-triggered flipflop |
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Mealy v. Moore machine: know/recognize the difference |
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Sequential design process: word problem -> state diagram -> state table -> flipflop equations |
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Designing with D, JK, and T flipflops: truth tables, characteristic equations, flipflop excitation tables |
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Vanilla register: parallel load too |
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Shift registers |
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Synchronous binary counters |
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Ripple counters: distinction from synchronous binary counters |
There will be no questions on section 6-9 which covers FPGAs.
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RAM: structure, definitions |
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Tri-state buffers |
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Coincident selection and RAM design |
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ROM: structure, combinational logic using |
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Tiling smaller RAM/ROM to build larger ones |
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PLA: structure, programming table, logic design using |
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PALs: structure, programming table, logic design using |
You must know the datapath model/diagram. You should be able to interpret RTL operations ala the homework as well. I won't ask you to build an ALU from scratch, but you should know the basic strucutre.
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Control/Datapath model |
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RTL operations: transfer, arithmetic, logic and shift |
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3 transfer architectures: muxes, busses, tri-state busses |
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Datapath structure: Reg file, Function unit, muxes |
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ALU: adder + logic structure, |
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Shifter: vanilla, barrel shifter |
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Control word |
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Pipelining: the basic concept, pipelining speedup equation |