Ripple Carry Adder Problems

The Ripple Carry Adder was fun, but it's slow:

	Total delay to add two n bit numbers is 2n + 2 gate delays
	So, delay adds as bit size increases

Solution: we'll sacrifice some of our design simplicity and hierarchy for speed.

The CLA

First step, completely separate the carry portion of the addition from the sum.

The "sum" part of the CLA is handled by the partial full adder (PFA):

Block diagram

Circuit implementation

The normal "Carry Out" bit found in the Full Adder is replaced with P and G outputs:

	Propagate P = A xor B P = 1: Carry is propagated from current bit to the next P = 0: Carry is blocked
	Generate G = AB G = 1: Carry out is 1, regardless of P G = 0: Carry is only propagated if P and carry from previous bit are 1

Get it? So for the i'th bit of the addition,

	the Carry Ci bit is generated (forced) if Gi is true
	the Carry Ci-1 is propagated to Ci if Pi and Ci-1 are both true (note the recursive definition)

So, let's look at come Carry bits:

Boolean equations In English

C0 - This is the input to the first PFA C0

C1 - Generate OR propagate the input carry C1 = G0 + (P0 C0)

C2 - Generate OR propagate previous carry... carry logic is expanded, not shared C2 = G1 + P1 C1    = G1 + P1 G0 + P1 P0 C0

C3 - Generate OR propagate previous carry... carry logic is expanded, not shared C3 = G2 + P2 C2 C3 = G2 + P2 (G1 + P1 G0 + P1 P0 C0) C3 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0

C4 - And so on... C4 = G3 + P3 C3 Expand the logic (this is getting large)...

Do you see the trick? Carry logic is replicated for each bit (as P/G) rather than reused. Size of the circuit is sacrificed for increased speed.

Reuse 4-bit CLA for 8, 16, 32, 64 bit addtion...

Summary

	Faster
	Bigger... more components
	A more complex design