"XOR-scuse me" Lab
Become familiar with and use the exclusive-or (XOR) gate to solve logic design problems |
7400 quad 2-input NAND | |
7486 quad 2-input XOR |
Pin layouts for these chips are attached.
For each lab problem, the following items are required:
A brief summary of the problem you are solving | |
A truth table (or SOP/POS form if appropriate) of the circuit that you are building | |
A logic diagram of the circuit that you are building... please use your templates! |
These items should be added to your report, as needed:
Show the steps (if any) you took to minimize or derive your circuit, such as: K-Maps, Boolean algebra, DeMorgan's Theorem, Consensus Theorem, etc. | |
Show your instructor (Bill) your circuit, if it's specified that you do so in the problem. There will always be at least one problem that requires inspection during a lab period. |
From our last lab, I think we can improve our performance by:
This lab focuses on the design of logic using XOR gates... from page 71, Section 2-7 in our text. Please complete each of the following parts:
Tie one of the inputs of the XOR gate to logic '1' and exercise the other input | |
Tie one of the inputs to logic '0' and exercise the other input | |
Tie the inputs together (both inputs the same value) |
For each special case, show the truth table, circuit diagram and comment on what common Boolean operation each case mimics.
Note: The final two steps aren't hard, rather a bit tricky... XORs "bend" many of our beloved logic design tools, namely Boolean algebra and K-Maps. You will have to recognize the XOR "pattern" with either your equation (A'B + AB') or K-Map (the checker-board pattern) during simplification. The next two problems exhibit these patterns.
Note: The full adder is discussed in our textbook on page 126; the truth table appears there. You can also get some solid hints on your design from there.